1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating an embedded dynamic random access memory (embedded DRAM).
2. Description of the Related Art
In the general fabricating process of embedded DRAM, in order to enhance the conductivity and reduce the contact resistance of source/drain region of the transistor in the logic circuitry region, a salicide is formed on the source/drain region of the substrate by self-aligned silicide process. The process to fabricate the bit line and the capacitor are then performed in the memory region when the salicide and the doped region are already formed in the logic circuitry region. The major material of the capacitor dielectric layer currently is ONO or Ta.sub.2 O.sub.5 and it is necessary to perform a high temperature thermal process to form the capacitor dielectric layer. However, the high temperature thermal process causes diffusion of ions in the doped region of the logic circuitry region. When the size of the device is gradually reduced, the short channel effect and punch through are easily occurred in the substrate due to the diffusion of the doped region and as a result, the reliability of the devices is degraded.
In addition, the high temperature process causes the agglomeration of the salicide and its volume is therefore reduced when the thermal process is performed after the formation of the salicide. The resistance of the salicide is hence increased to lower the performance of the salicide since agglomeration.